Metal-semiconductor-field effect transistor (MESFET) with lightly doped drain contact region for higher voltage breakdown

ABSTRACT

A MESFET is disclosed wherein a gallium arsenide semiconductor material is doped. The doping magnitude differs in the source area, drain area, and in the gate area. An increase of the dielectric strength without an increase of parasitic resistances is provided. In the manufacture of the MESFET, shadowing techniques are employed to vary the doping magnitudes.

This is a division of application Ser. No. 038,895, filed May 14, 1979now U.S. Pat. No. 4,325,747.

BACKGROUND OF THE INVENTION

The invention relates to a metal-semiconductor-field effect transistor(MESFET).

Field effect transistors are known in which the gate electrode issupported directly on the semiconductor surface between the source areaand the drain area and forms a metal-semi-conductor (Schottky) contact.Such field effect transistors are designated as MESFET's. Such a MESFETis built up, for example, on a semiconductor layer located on aninsulating substrate, whereby the layer thickness generally amounts from0.1 to 0.5 μm and the doping of this semiconductor material has amagnitude of about 10¹⁷ particles per cm³. The contact areas for sourceand drain generally have a distance from one another of about 3 to 7 μmand a strip-shaped Schottky-contact area with a width of 0.5 to 2 μmlies between these two areas. Gallium arsenide is preferably consideredas the semiconductor material for MESFET's. All the three areas have thesame conductivity type.

For power MESFET's, the parasitic resistances at the contacts and in thesemiconductor layer are to be kept small and a large voltage betweensource and drain area can be applied without an electrical puncture orbreakthrough occurring in the semiconductor layer between these areas.

Up to now, this problem was solved in such manner that one provided arelatively thick semiconductor layer and applied the contact strip forthe gate in a somewhat recessed area of the semiconductor layer. It wasthereby achieved that the semiconductor layer has a small thicknessbelow the contact strip serving as the gate required for the function ofa MESFET. The thicker layer parts beyond the gate area contribute to areduction of the parasitic resistances. It has likewise been suggestedto provide both the source area as well as the drain area with anincreased doping of, for example, 10¹⁸ particles per cm³. Accordingly,the contact resistance between the material of the semiconductor layerand the contact metallization located thereon was reduced by the ohmicjunction, the path resistance was reduced in the semiconductor layer,and higher voltages could be applied. Moreover, by so doing, the noiseproperty could also be improved. Concerning this state of the art, thepublications IEEE MT-24, 1976, 312-317; Proceedings of the 6thInternational Symposium concerning Gallium arsenide and RelatedCompounds, St. Louis (1976), Pages 262-270; and IEEE ED-24 (1977),1129-1130 all incorporated herein by reference, are pertinent.

According to the IEEE ISSCC Digest of Technical Papers (1978), 118-119,incorporated by reference, good power MESFET's can also be achieved whenthe doping in the source area and in the drain area lies at only about10¹⁷ particles per cm³ and the thickness of the semiconductor layer isselected correspondingly large.

SUMMARY OF THE INVENTION

An object of the present invention is to optimize a MESFET, particularlyof the last-mentioned type, when it functions as a power-MESFET.

This object is inventively achieved in a MESFET wherein the drain areaor zone is less highly doped than the gate area and the gate area isless highly doped than the source area. In the manufacturing of suchmetal-semiconductor field effect transistor, a mask is applied over aportion of a surface of the semiconductor layer where the drain zone isto be formed. A portion of the semiconductor layer adjacent the coveredsurface portion thereof, (i.e., a portion adjacent to an edge of themask), is stripped away so as to create a step at such mask edge. Ionimplantation for doping of the semiconductor layer at the uncoveredsurface thereof is then carried out from a first direction while themask covers the drain zone but not the source and gate zones (i.e., sothat only the source and gate zones are doped). Next, ion implantationis carried out from a second direction (generally at an oblique angle tothe first direction) so that only the source zone is doped. During thissecond ion implantation step, the gate zone is not doped because of theshadowing effect provided by the mask edge and, of course, the drainzone is not doped because it is still covered by the mask. Either priorto the application of the mask or after the removal of the mask, allthree zones, drain, gate and source zones, are commonly doped. Thiscommon doping of all three zones can occur prior to the firstimplantation step (i.e., prior to the doping of only the source and gatezones) or after the second implantation (i.e., when the mask isremoved). In this manner, the resultant MESFET has a source zone withgreater doping than a gate zone thereof while such gate zone has agreater doping than a drain zone thereof.

The invention proceeds from the consideration that the largest electricfield strengths which could lead to a puncture occur in the MESFETbetween the gate and the drain area. It is therefore advantageous toprovide a lower doping concentration in this area. It was determinedthat the electric resistance between the gate and drain areas therebyresulting has a relatively small influence on the amplification effect,and comparatively smaller than a resistance between the gate and thesource area. For this reason, a degenerated (N⁺) doping is alsoadvantageous for the source area according to a feature of theinvention. Thus, the doping condition N_(D) <N_(G) <N_(S) is to befulfilled for the three areas of the drain, of the gate and of thesource which have distances from one another which lie at a few μm.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a MESFET of the invention; and

FIGS. 2 through 6 show individual process steps in manufacturing theMESFET.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An inventive MES-field effect transistor located in a semiconductorlayer 2 is designated 1. The semiconductor layer 2 preferably consistingof gallium arsenide is located on an electrically insulating substratebody 3. In particular highimpedance gallium arsenide or gallium arsenidewhich has been made semi-insulating is employed.

A drain area referenced with 11 is indicated by means of shading. On thedrain area a metal contact referenced 12 is provided for the currentsupply. As a rule, the contact 12 is part of a printed line, forexample, of a gold alloy, serving as a feed. An area of thesemiconductor layer 2 functioning as a source area is noted by a furthershading 13. A contact for this area is applied thereon corresponding tocontact 12. 16 designates a metal strip, already mentioned above, whichforms gate (Schottky) metal-semiconductor contact on the semiconductorlayer 2. A gate area 15, which is again noted by means of shading andwhich functions as an electrical control, is formed beneath this metalstrip 16. This results because the different potentials at the sourceand drain areas are different than the potential of strip 16.

According to the invention, a doping distribution is provided in theMESFET 1, for example, for gallium arsenide, in which the doping in thedrain area 11 amounts to less than 10¹⁷ particles per cm³. A doping of,for example, 1 to 4 · 10¹⁷ particles per cm³ is provided in the gatearea 15. On the other hand, a doping of 1 to 8 · 10¹⁸ particles per cm³is present in the source area 13. For a lower limit of the doping of thedrain area 11, care must be taken that sufficient electricalconductivity is still present so that an unallowably large parasiticresistance does not occur. For the upper limit of the doping of thesource area 13, care must be taken to see that the doping is not largesuch that crystal lattice defects compensate or at least negativelyinfluence the intended doping. N doping for the areas or, respectively,regions is preferably provided, for example, for gallium arsenide.

As a rule, a lower doping of 10¹⁵ particles per cm³ or less is to beprovided beyond the areas 11, 13 and 15. There, however, a doping canalso be completely omitted or the layer can be etched away.

The manufacture of a MESFET in accordance with the invention preferablyensues as follows.

FIG. 2 shows the aforementioned substrate body 3 on which thesemiconductor layer 2 consisting of, for example, gallium arsenide,silicon, or indium phosphide is located. In a first process step, thissemiconductor layer 2 is first doped to such a degree, for example, inthe manufacturing process of layer 2 or by means of a succeedingdiffusing-in or of an entire surface ion implantation, that the dopingpresent for the drain area 11 is not more than 10¹⁷ particles per cm³.

The arrows 21 indicate, for example, an ion implantation process for theproduction of the doping of this process step.

FIG. 3 shows the substrate body 3 with the semiconductor layer 2 locatedon it and upon which a coating or mask 22 is located which covers aportion of the surface of the semiconductor layer 2. Therefore, the areaof the semiconductor layer 2 is covered in which the drain area 11 islocated. This covering 22 can be produced with the assistance of a metalwhich is sputtered on or also by means of a photosensitive resist.

FIG. 4 shows the result of a further process by which a superficialerosion of the semiconductor layer 2 has been achieved. The thickness ofthe cut amounts, for example, to 20 nm. This leads to a step referenced23 which, in a later processing step, serves as a recognition of thelimit of the drain area 11 indicated by shading.

FIG. 5 again shows the substrate 3 with the semiconductor layer 2located thereon and on which the coating 22 is still located. In thenext process step, the semiconductor layer 2 is now further doped, inthe area not covered by the covering 22, to the extent of the gate areadoping of 1 to 4 · 10¹⁷ particles per cm³. This doping, for example, canagain be undertaken with the help of an implantation. For thisimplantation, one must take care that no significant shadow effectensues because of the covering 22. The implantation direction can becarried out as indicated by arrows 24 and 25 (and at directions lyinginbetween).

The still higher doping of the source area with 1 to · 10¹⁸ particlesper cm³ is undertaken in a further implantation step with animplantation direction as indicated by arrows 26. For this implantationdirection corresponding to the arrows 26, care must be taken that, as afunction of the thickness of the shadowing edge of the covering 22, thedoping is such that the shadowing effect causes an intermediate space toremain as seen in step 26 (toward the left in FIG. 6) which is notfurther doped (gate area 15 of the transistor according to FIG. 1).

In further process steps--not illustrated--the covering 22 is thenremoved and the contacts 12, 14 and 16 are applied.

In the execution of the inventive manufacturing process withimplantation in all process steps, only the implantation direction needbe changed between the individual process steps, for example, by meansof angular rotation of the substrate body on its carrier. The dopingsubstance can always remain the same.

The manufacturing process of an inventive MESFET can be changedaccording to a variation of the manufacturing process described above insuch manner that the sequence of the doping steps of FIGS. 2, 5 and 6 isinterchanged. For example, the implantation 26 of the source area (FIG.6) can be undertaken first with the implantation according to FIG. 5then being undertaken subsequently. According to another variation, theimplantation 21 corresponding to that of FIG. 2, for example, can beundertaken after the process step of FIG. 6, namely, after removal ofthe covering 22. One need only take care that the inventive doping stepsrespectively exist in the individual areas or, respectively, regions inthe final result.

According to a further embodiment of the inventive MESFET or,respectively, of the inventive manufacturing process, during or afterthe process step of FIG. 2, a merely superficial implantation, i.e. animplantation 40 existing in the semiconductor layer 2 with only aminimum penetration depth as shown in dotted lines in FIG. 2 isundertaken which leads to a (superficial) high doping in the magnitudeof 1 to 8 · 10¹⁸ particles per cm³. Such a superficial additional dopingleads to a reduction of the contact resistance between the metal contact12 and the otherwise weakly doped drain area 11. The penetration depthof this increased doping is selected, in particular, in such manner thatit does not exceed the dimension of the step shown in FIG. 2, so thatthis increased surface doping, i.e. this highly doped semiconductormaterial of the surface layer of the semiconductor layer 2 is alreadyremoved again by means of the process step of FIG. 4 outside of thedrain area. A residue of the highly doped surface layer can also bestripped immediately before the application of the metal strip 16.

Although various minor modifications may be suggested by those versed inthe art, it should be understood that I wish to embody within the scopeof the patent warranted hereon, all such embodiments as reasonably andproperly come within the scope of my contribution to the art.

I claim as my invention:
 1. A metal-semiconductor field effecttransistor (MESFET), comprising: a semiconductor material having highlydoped source, drain and gate areas therein; the three areas having thesame conductivity type and the gate area being positioned between thedrain and source areas and being less highly doped than the source area;and a doping of the drain area being lower than the doping of the gatearea.
 2. A metal-semiconductor field effect transistor according toclaim 1 in which the semiconductor material comprises gallium arsenide.3. A metal-semiconductor field effect transistor according to claim 1 inwhich the semiconductor material is a thin layer located on a substratebody, drain, gate, and source contacts are all located on a surface ofthe thin layer opposite the substrate body, and a step is provided on asurface of the layer between the drain and gate areas, the gate andsource areas being located at a lower level of the step.
 4. Ametal-semiconductor field effect transistor according to claim 1 whereinthe doping is N-doping.
 5. A metal-semiconductor field effect transistor(MESFET), comprising: an insulating layer; a semiconductor layerarranged on the insulating layer; contiguous source, gate, and drainzones formed in the semiconductor layer which are all doped with thesame conductivity type; electrodes positioned over each of the source,gate and drain zones; a doping of the source zone being greater than adoping of the gate zone and a doping of the gate zone being higher thana doping of the drain zone, the change of doping from the source to thegate and the gate to the drain zones being provided in a contiguousfashion.